Conventionally, a 12-transistor (12T) NVSRAM cell is made of one 6T SRAM cell and one 6T Flash cell. Each Flash cell comprises a paired 3T flash strings. Each flash string comprises three HV transistors with one flash transistor (1T) in the middle sandwiched by one top (1T) and one bottom (1T) HV Select transistors.
The conventional 12T NVSRAM uses a 2-step Write operation that uses FN-channel Erase scheme with flash gate tied to a negative voltage VNN as a first step to either decrease flash cell's channel threshold level Vt to Vt0≦−2V initially followed by a second step of FN-channel Program scheme with the flash gate tied to a positive voltage VPP to conversely increase flash cell's Vt to a value of Vt1≧+2V to obtain a large value of Vt difference from a erased state to a programmed state ΔVt12≧4V initially. With this big ΔVt12≧4V, a superior NVSRAM Recall operation can be achieved at low VDD operation. For example, VDD can be as low as 1.2V.
But, one major disadvantage of the above 12T NVSRAM cell is the big cell size. A 6T HV Flash cell takes more silicon layout than a 6T LV SRAM cell layout typically. After a long P/E endurance cycle, the distance of the gap of ΔVt of Erase and Program Vt becomes smaller, thus the big cell size of 12T NVSRAM may result in unreliable cell operations, especially for low 1.2V VDD operation.
Therefore, an improved NVSRAM cell design with reduced cell size by cutting transistor numbers or enhancing sharing in circuit design along with proper write operation and recall operation are desired and become objectives of the present invention.